1. Field of the Invention
The invention relates to a clock switcher electrical circuit which allows for switching between clock signals of a plurality of clock signal sources, and, more particularly, such a clock switcher circuit which allows for switching between clock signals of the plurality of clock signal sources without resulting in arbitrarily short clock pulses.
2. Description of the Related Art
In digital electronic circuits, clock sources provide pulsed timing signals which allow for appropriate timing and ordering of events occurring within the circuits. It is desirable in certain of those circuits to allow the clock source for the circuit to be switched from time to time between any of a plurality of clock sources. It is hard, if not impossible, to exactly synchronize timing signals generated by more than one clock. Therefore, switching between clock sources can result in arbitrarily shortened or lengthened pulses during the switch.
The problem with arbitrarily shortened or lengthened pulses during a switch between clock sources is that operations within particular circuits may necessarily depend upon an absolute time, i.e., pulse length, for appropriate completion of the steps of those operations. For example, in the case of a shortened clock pulse during a switch between clock sources, some flip flops of a certain circuit block will see the pulse but others may not since the pulse is shorter than the normal pulse. This problem could be prevented if one could sufficiently study the circuit block to confirm that all flip flops will see every possible arbitrarily shortened pulse; however, such a study is not practical in most cases and may even be impossible. A lengthened pulse typically does not present the problems which may result in the case of a shortened pulse. It is, therefore, in most cases suitable to have arbitrarily lengthened pulses and still guarantee appropriate circuit block operation. Arbitrarily shortened clock pulses, on the other hand, are a problem.
Others have attempted to resolve the problem of arbitrarily shortened clock pulses during switching between clock sources. One example of such an attempt disclosed in U.S. Pat. No. 5,099,140 to Mudgett. That patent discloses a synchronizing circuit, responsive to a detector for disabling a gate in synchronism with the old clock source and thereafter enabling the gate in synchronism with a new clock source. In the case of that solution, synchrony of the signals from the clock sources is mimicked by the particular circuit due to the disabling and then enabling of the gate. Though the mimicking circuitry of this patent may work in certain applications, it may not be suitable for others.
An example of a circuit block in which switching between clock sources may be necessary is a circuit block which does data formatting for a communication channel. In such a communication channel, data bytes that are to be communicated must appear at the right place within the circuit block at the right relative time. When such a circuit block must switch between clock sources, the various clock sources must in some manner be interrelated so that switching between the clock sources does not disrupt the timing of the circuit block, causing disruption of appropriate data formatting by the block.
In a more specific example of this type communication channel, the protocol on the communication channel dictated by the circuit block requires that the block, at times, be the timing master dictating the timing of the communication channel and, at other times, be the timing slave. When the block is the timing slave in this example communication channel, the timing for the block comes from clock recovery circuitry which is a phase-locked loop that recovers the timing from the channel. Because the channel specifies the timing in this instance when the block is the timing slave, it may be necessary to switch between clocks from time to time to achieve the particular timing designated by the clock recovery circuitry. When the block in this example serves as the timing master, however, the block uses whatever clock is providing signals at the time and no switching between clocks is then necessary. So with such a circuit block for a communication channel, the block must be run at various times on one of two or more different clocks and must periodically switch between those different clocks.
The present invention provides a clock switcher circuit which eliminates the possibility of arbitrarily short clock pulses upon switching between clocks. The present invention, thus, provides an improved apparatus and method for switching between clock sources which provide signals to a circuit block.